Clock and data recovery (CDR) circuits are widely used when a data signal is sent across a communications link without an accompanying dedicated clock signal. CDR circuits typically use a phase-locked loop (PLL) to determine, from the transitions between physical data values, the exact frequency at which data is arriving and the optimum phase at which to sample the incoming data. A typical PLL includes a phase detector, a loop filter, and a voltage controlled oscillator (VCO) that produces a VCO signal. The phase detector compares an input signal with a portion of the VCO signal and produces an output that indicates the relative phase of the two signals. The output is provided to the loop filter and in response, the loop filter produces a voltage that causes the phase of the VCO signal to move closer to the input signal. A portion of the VCO signal is then looped back to the phase detector in a continuous process. When the loop is locked, the frequency and phase of the VCO signal track the frequency and phase of the input signal.
A central component in ensuring signal lock is the phase detector. There are generally two classes of phase detectors, analog and digital. Digital phase detectors (also referred to as “binary,” “up/down,” or “bang-bang” phase detectors) compare the phase of the input and VCO signals and output a binary indication of the relative phase of the two signals (i.e., whether the recovered VCO signal is early or late). The indication of the relative phase is typically provided as binary early and late signals.
Transmitting data across a communication link tends to cause the digital phase detector to experience a direct current (DC) offset. If the DC offset grows too large, it can negatively affect the performance of the PLL. One technique that has been used to compensate for DC offset involves using DC feedback around an input amplifier to insure that the input amplifier presents data to the sampling mechanism of the digital phase detector with a DC component that has been reduced by the gain of the feedback loop. Drawbacks to this approach include that it does not correct for the offset of the sampler and it requires balanced data (i.e., data with equal numbers of ones and zeros). Even with data that is statistically balanced, the low pass filter in the PLL must have a very long time constant (which often means it is physically large) to be immune to running disparities in the data. Another technique that has been used to compensate for DC offset involves using a sampling mechanism whose offset can be trimmed. This technique requires the input to the sampling mechanism to be removed from the data and the differential inputs be shorted in order to measure and adjust for the offset, which is not always possible or practical.
In view of this, what is needed is a technique for correcting for DC offset in a PLL circuit that provides the desired performance and is efficient to implement.